深圳市昌宏瑞科技有限公司

1.General Description
The RTL8685PB is an integrated System-on-a-Chip(SoC) with dual CPU MIPS interAptivTM andRLX5281,a VDSL2/ADSL2+ Discrete Multi-tone (DMT) data-pump， a PTM/ATM,hardware-basedATM Segmentation and Reassembly (SAR)， a packet forwarding engine,and with USB and PCIEinterfaces.
The RTL8685PB supports the MIPS interAptivTM with clock rate up to 1GHz dual core(RTL8685PB-VA5 for 1GHz, RTL8685PB-VF5 for 750MHz) and integrates an RLX5281 processor withclock rate up to 500MHz dual core with DSP for VolP.A standard 5-signal P1149.1 compliant EJTAGtest interface is supported for CPU (RLX5281 and MIPS IA) testing and software development.
The RTL8685PB is designed with the Realtek RTL8275-VS (VDSL2/ADSL2+ Analog Front End) forVDSL2/ADSL2+ applications.
A built-in packet forwarding engine can perform wire-speed network traffic forwarding. The CPU may beused to handle upper layer functions,such as DHCP, HTTP, and various other profocols, and to operatewith a hardware accelerated forwarding engine.
The RTL8685PB provides five physical layer transceivers for 10Base-T, 100Base-TX, and 1000Base-TX.These ports support flexible IEEE 802.3x full-duplex flow control and optional half-duplex backpressurecontrol.For full-duplex， standard JEEE 803.3x flow control will enable pause ability only when bothsides of UTP have auto-negotiation ability as well as enabled pause ability. It also provides an optionalforced mode IEEE 802.3x full-duplex flow control and MDIMDIX auto crossover function.
The RTL8685PB requires only a single 25MHz crystal clock ioput for the system, and a 3.3V and 1.1external power supply.
The RTL8685PB supports 16550-compatible peripheral interfaces UARTs,and is provided in aTFBGA-292 package.